ADSP-2185
Parameter
Bus Request/Grant
Timing Requirements:
t
BH
BR
Hold after CLKOUT High
1
t
BS
BR
Setup before CLKOUT Low
1
Switching Characteristics:
t
SD
CLKOUT High to
xMS, RD, WR
Disable
t
SDB
xMS, RD, WR
Disable to
BG
Low
t
SE
BG
High to
xMS, RD, WR
Enable
t
SEC
xMS, RD, WR
Enable to CLKOUT Hig
t
SDBH
xMS, RD, WR
Disable to
BGH
Low
2
t
SEH
BGH
High to
xMS, RD, WR
Enable
2
0.25 t
CK
+ 2
0.25 t
CK
+ 17
0.25 t
CK
+ 10
0
0
0.25 t
CK
鈥?7
0
0
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Unit
NOTES
xMS
=
PMS, DMS, CMS, IOMS, BMS
1
BR
is an asynchronous signal. If
BR
meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the
ADSP-2100 Family User鈥檚 Manual
for
BR/BG
cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
t
BH
CLKOUT
BR
t
BS
CLKOUT
PMS, DMS
BMS, RD
WR
t
SD
t
SEC
BG
t
SDB
t
SE
BGH
t
SDBH
t
SEH
Figure 16. Bus Request鈥揃us Grant
REV. 0
鈥?9鈥?/div>
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