您的位置：维库电子市场网 > Datasheet > CS5530A

CS5530A Datasheet

  • CS5530A

  • National Semiconductor [Geode CS5530A I/O Companion Multi-F...

  • 3879.27KB

  • NSC

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

Geode鈩?CS5530A
Signal Definitions
(Continued)
2.2
2.2.1
SIGNAL DESCRIPTIONS
Reset Interface
Pin
No.
C14
Pin
Type
O
Description
PCI Reset
PCI_RST# resets the PCI bus and is asserted while POR# is asserted, and
for approximately 9 ms following the deassertion of POR#.
Signal Name
PCI_RST#
POR#
K24
I
Power On Reset
POR# is the system reset signal generated from the power supply to indi-
cate that the system should be reset.
CPU_RST
K25
O
CPU Reset
CPU_RST resets the CPU and is asserted while POR# is asserted, and for
approximately 9 ms following the deassertion of POR#. CLK_14MHZ is
used to generate this signal.
2.2.2
Clock Interface
Pin
No.
J26
Pin
Type
I
(SMT)
I
Description
PCI Clock
The PCI clock is used to drive most circuitry of the CS5530A.
Television Clock
The TVCLK is an input from a digital NTSC/PAL converter which is option-
ally re-driven back out onto the DCLK signal under software program con-
trol. This is only used if interfacing to a compatible digital NTSC/PAL
encoder device.
Signal Name
PCICLK
TVCLK
B2
DCLK
A10
O
DOT Clock
DOT clock is generated by the CS5530A and typically connects to the pro-
cessor to create the clock used by the graphics subsystem. The minimum
frequency of DCLK is 10 MHz and the maximum is 200 MHz. However,
when DCLK is used as the graphics subsystem clock, the Geode processor
determines the maximum DCLK frequency.
ISACLK
AD6
O
ISA Bus Clock
ISACLK is derived from PCICLK and is typically programmed for approxi-
mately 8 MHz. F0 Index 50h[2:0] are used to program the ISA clock divisor.
CLK_14MHZ
P24
I
(SMT)
14.31818 MHz Clock
This clock is used to generate CPU_RST to the Geode processor. DOT
clock (DCLK) is also derived from this clock.
USBCLK
This input is used as the clock source for the USB. In this mode, a 48 MHz
clock source input is required.
32 KHz Clock
CLK_32K is a 32.768 KHz clock used to generate reset signals, as well as to
maintain power management functionality. It should be active when power is
applied to the CS5530A.
CLK_32K can be an input or an output. As an output CLK_32K is internally
derived from CLK_14MHZ. F0 Index 44h[5:4] are used to program this pin.
USBCLK
W1
I
(SMT)
CLK_32K
AE3
I/O
Revision 1.1
23
www.national.com

CS5530A相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2025 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！