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CS5530A Datasheet

  • CS5530A

  • National Semiconductor [Geode CS5530A I/O Companion Multi-F...

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Geode鈩?CS5530A
Functional Description
(Continued)
3.3.3.1 DCLK Programming
The PLL contains an input divider (ID), feedback divider
(FD) and a post divider (PD). The programming of the
dividers is through F4BAR+Memory Offset 24h (see Table
3-9 on page 53). The maximum output frequency is 300
MHz. The output frequency is given by equation #1:
Equation #1:
DCLK = [CLK_14MHZ * FD] 梅 [PD *ID]
Condition:
140 MHz < [DCLK * PD] < 300 MHz
Where:
CLK_14MHZ is pin P24
FD is derived from N see equation #2 and #3:
PD is derived from bits [28:24]
ID is derived from bits [2:0]
Equation #2:
If FD is an odd number then: FD = 2*N +1
Equation #3:
If FD is an even number then: FD = 2*N +0
Where:
N is derived from bits [22:12]
+1 is achieved by setting bit 23 to 1.
+0 is achieved by clearing bit 23 to 0.
Example
Define Target Frequency:
Target frequency = 135 MHz
Satisfy the 鈥淐ondition鈥?
(140 MHz < [DCLK * PD] < 300 MHz)
140 MHz < [135 MHz * 2] < 300 MHz
Therefore PD = 2
Solve Equation #1:
DCLK = [CLK_14MHZ * FD] 梅 [PD *ID]
135 = [14.31818 * FD] 梅 [2 * ID]
135 = [7.159 * FD] 梅 ID
18.86 = FD 梅 ID
Guess: ID = 7, Solve for FD
FD = 132.02
Solve Equation #2 or #3:
FD = 2*N +1 for odd FD
FD = 2*N +0 for even FD
FD is 132, therefore even
132 = 2*N +0
N = 66
Summarize:
PD = 2: Bits [28:24] = 00111
ID = 7: Bits [2:0] = 101
N = 66: Bits [22:12] = 073h (found in Table 3-10), clear
bit 23
Result:
DCLK = 135
The BIOS has been provided with a complete table of divi-
sor values for supported graphics clock frequencies. Many
combinations of divider values and VCO frequencies are
possible to achieve a certain output clock frequency. These
BIOS values may be adjusted from time to time to meet
system frequency accuracy and jitter requirements. For
applications that do not use the GX-series processor鈥檚
graphics subsystem, this is an available clock for general
purpose use.
The transition from one DCLK frequency to another is not
guaranteed to be smooth or bounded; therefore, new
divider coefficients should only be programmed while the
PLL is off line in a situation where the transition character-
istics of the clock are 鈥渄on't care鈥? The steps below
describe (in order) how to change the DCLK frequency.
1)
2)
3)
4)
5)
Program the new clock frequency.
Program Feedback Reset (bit 31) high and Bypass
PLL (bit 8) high.
Wait at least 500 碌s for PLL to settle.
Program Feedback Reset (bit 31) low.
Program Bypass PLL (bit 8) low.
www.national.com
52
Revision 1.1

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