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CS5530A Datasheet

  • CS5530A

  • National Semiconductor [Geode CS5530A I/O Companion Multi-F...

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  • NSC

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Geode鈩?CS5530A
Functional Description
(Continued)
Table 3-32. GPIO Pin Configuration/Control Registers (Continued)
Bit
Description
GPIO Control Register 1 (R/W)
Reset Value = 00h
F0 Index 92h
7
6
GPIO7 Edge Sense for Reload of General Purpose Timer 2:
Selects which edge transition of GPIO7 causes
GP Timer 2 to reload. 0 = Rising; 1 = Falling (Note 2).
GPIO6 Enabled as Lid Switch:
Allow GPIO6 to act as the lid switch input. 0 = GPIO6; 1 = Lid switch.
When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI.
The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 87h/F7h[3].
If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid鈥檚 position.
5
4
3
2
GPIO2 Edge Sense for SMI:
Selects which edge transition of the GPIO2 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 2 must be set to enable this bit.
GPIO1 Edge Sense for SMI:
Selects which edge transition of the GPIO1 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 1 must be set to enable this bit.
GPIO0 Edge Sense for SMI:
Selects which edge transition of the GPIO0 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 1 must be set to enable this bit.
Enable GPIO2 as an External SMI Source:
Allow GPIO2 to be an external SMI source and generate an SMI on either a
rising or falling edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable (Note 3).
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 87h/F7h[7].
1
Enable GPIO1 as an External SMI Source:
Allow GPIO1 to be an external SMI source and generate an SMI on either a
rising- or falling-edge transition (depends upon setting of bit 4). 0 = Disable; 1 = Enable (Note 3).
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 87h/F7h[6].
0
Enable GPIO0 as an External SMI Source:
Allow GPIO0 to be an external SMI source and generate an SMI on either a
rising or falling edge transition (depends upon setting of bit 3). 0 = Disable; 1 = Enable (Note 3)
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 87h/F7h[5].
Notes:
1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).
2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both.
3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the
system from Suspend when the clocks are stopped.
F0 Index 97h
7
6
5
4
3
Bit 3 must be set to enable this bit.
GPIO5 Edge Sense for SMI:
Selects which edge transition of the GPIO5 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 2 must be set to enable this bit.
GPIO4 Edge Sense for SMI:
Selects which edge transition of the GPIO4 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 1 must be set to enable this bit.
GPIO3 Edge Sense for SMI:
Selects which edge transition of the GPIO3 pin generates an SMI. 0 = Rising; 1 = Falling.
Bit 0 must be set to enable this bit.
Enable GPIO7 as an External SMI Source:
Allow GPIO7 to be an external SMI source and to generate an SMI on either a
rising or falling edge transition (depends upon setting of bit 7). 0 = Disable; 1 = Enable.
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 84h/F4h[3].
2
Enable GPIO5 as an External SMI Source:
Allow GPIO5 to be an external SMI source and to generate an SMI on either a
rising or falling edge transition (depends upon setting of bit 6). 0 = Disable; 1 = Enable.
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 84h/F4h[2].
1
Enable GPIO4 as an External SMI Source:
Allow GPIO4 to be an external SMI source and to generate an SMI on either a
rising- or falling-edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable.
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status reporting is at F0 Index 84h/F4h[1].
GPIO Control Register 2 (R/W)
Reset Value = 00h
GPIO7 Edge Sense for SMI:
Selects which edge transition of the GPIO7 pin generates an SMI. 0 = Rising; 1 = Falling.
Revision 1.1
77
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