SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

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endpoint data buffers and the codec port interface. The USB endpoint number and direction can be programmed for

each DMA channel. Also, the codec port interface time slots to be serviced by each DMA channel can be

programmed.

2.1.13 Codec Port Interface

The TAS1020A provides a configurable full duplex bidirectional serial interface that can be used to connect to a codec

or other external device types for streaming USB isochronous data. The interface can be configured to support

several different industry standard protocols, including AC 鈥?7 1.X, AC 鈥?7 2.X, AIC, and I

S. The TAS1020A also has

a general-purpose mode to support other protocols.

2.1.14 I

C Interface

The I

C interface logic provides a two-wire serial interface that the 8052 MCU can use to access other ICs. The

TAS1020A is an I

C master device only and supports single byte or multiple byte read and write operations. The

interface can be programmed to operate at either 100 kbps or 400 kbps. In addition, the protocol supports 8-bit or

16-bit addressing for accessing the I

C slave device memory locations. The TAS1020A supports I

C wait states. This

means slaves can assert wait state on the I

C bus by pulling the SCL line low.

2.1.15 General

Purpose IO Ports (GPIO)

The TAS1020A provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The two ports

are port 1 and port 3. Port 1 provides true GPIO capability. Each bit of port 1 can be independently used as either

an input or output, and consists of an output buffer, an input buffer, and a pullup resistor. Some of the bits of port 3

also provide true GPIO capability, but, in addition, some of the bits of port 3 also provide alternate input and output

uses. An example of this is P3.2, which is used as the external interrupt (XINT) input to the TAS1020A. A detailed

description of the alternate uses of some of the port 3 bits is presented in Section 2.2.11.

The pullup resistors for port 1 and port 3 can be disabled by bits P1PUDIS and P3PUDIS respectively in the on-chip

2.1.16 Interrupt Logic

The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0 (INTO) input

on the 8052 MCU core accordingly. All of the TAS1020A internal interrupt sources and the external interrupt (XINT)

input are ORed together to generate the INT0 signal. An interrupt vector register is used by the MCU to identify the

interrupt source.

2.1.17 Reset Logic

An external master reset (MRESET) input signal that is asynchronous to the internal clocks can be used to reset the

TAS1020A logic. In addition to this master reset, the TAS1020A logic can also be reset by a USB reset from the host

PC if bit FRSTE in the on-chip register USBCTL is set to 1. The TAS1020A also provides a reset output (RSTO) signal

that can be used by external devices. This signal is asserted when either a master reset occurs or when a USB reset

occurs and FRSTE is set to 1.

2.2 Device Operation

The operation of the TAS1020A is explained in the following sections. For additional information on USB, refer to the

Universal Serial Bus Specification, Version 1.1.

2鈥?

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