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SLES003A Datasheet

  • SLES003A

  • Texas Instruments [USB Streaming Controller]

  • 487.38KB

  • TI

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A.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte)
(ACGCAPL 鈥?Address FFE4h)
The adaptive clock generator MCLK capture register (low byte) contains the least significant byte of the 16-bit codec
master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. The value of
a16-bit free running counter, which is clocked with the MCLK signal, is captured at the beginning of each USB frame.
The source of the MCLK signal used to clock the 16-bit timer can be selected to be either the MCLKO signal or the
MCLKO2 signal. See Section 2.2.6 for the operation details of the adaptive clock generator.
Bit
Mnemonic
Type
Default
BIT
7:0
MNEMONIC
CAP(7:0)
7
CAP7
R
0
6
CAP6
R
0
NAME
ACG MCLK capture
5
CAP5
R
0
4
CAP4
R
0
3
CAP3
R
0
2
CAP2
R
0
DESCRIPTION
The ACG MCLK capture bit values are updated by hardware each time a USB start of frame
occurs. This register contains the least significant byte of the 16-bit value.
1
CAP1
R
0
0
CAP0
R
0
A.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte)
(ACGCAPH 鈥?Address FFE3h)
The adaptive clock generator MCLK capture register (high byte) contains the most significant byte of the 16-bit codec
master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs.
Bit
Mnemonic
Type
Default
BIT
7:0
MNEMONIC
CAP(15:8)
7
CAP15
R
0
6
CAP14
R
0
NAME
ACG MCLK capture
5
CAP13
R
0
4
CAP12
R
0
3
CAP11
R
0
2
CAP10
R
0
DESCRIPTION
The ACG MCLK capture bit values are updated by hardware each time a USB start of frame
occurs. This register contains the most significant byte of the 16-bit value.
1
CAP9
R
0
0
CAP8
R
0
A.5.3.6 Adaptive Clock Generator2 Frequency Register (Byte 0) (ACG2FRQ0 鈥?Address FFF9h)
The adaptive clock generator control registers ACG2FRQ0, ACG2FRQ1, and ACG2FRQ2, contain the 24-bit value
used to program the ACG2 frequency synthesizer.
Bit
Mnemonic
Type
Default
BIT
7:0
MNEMONIC
FRQ(7:0)
7
FRQ7
R/W
0
6
FRQ6
R/W
0
NAME
ACQ2 frequency
5
FRQ5
R/W
0
4
FRQ4
R/W
0
3
FRQ3
R/W
0
2
FRQ2
R/W
0
DESCRIPTION
The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency
synthesizer.
1
FRQ1
R/W
0
0
FRQ0
R/W
0
A.5.3.7 Adaptive Clock Generator2 Frequency Register (Byte 1) (ACG2FRQ1 鈥?Address FFF8h)
Bit
Mnemonic
Type
Default
BIT
7:0
MNEMONIC
FRQ(15:8)
7
FRQ15
R/W
0
6
FRQ14
R/W
0
NAME
ACQ2 frequency
5
FRQ13
R/W
0
4
FRQ12
R/W
0
3
FRQ11
R/W
0
2
FRQ10
R/W
0
DESCRIPTION
The ACG2 frequency bit values are set by the MCU to program the ACG2 frequency
synthesizer.
1
FRQ9
R/W
0
0
FRQ8
R/W
0
A鈥?6

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