SLES003A Datasheet

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In addition, although not shown in Figure 2鈥?, each master clock is assigned its own CSYNC generator, with the

length and polarity of each CSYNC separately programmable.

SOF

PSOF

ACG1DCTL[7:4]

4

6 MHz

Oscillator

PLL

Frequency 1

Synthesizer

Divide

by M1

ACG2DCTL[7:4]

4

Frequency 2

Synthesizer

Divide

by M2

ACG1DCTL[2:0]

3

MCLKI

Divide

by I

ACGCTL[1]

ACGCTL[0]

ACGCTL[7]

MCLK02

Divide by B2

CPTRXCNF4 [2:0]

CSCLK2

ACGCTL[4]

ACGCTL[3]

ACGCTL[6]

MCLK0

Divide by B

CPTCNF4 [2:0]

CSCLK

16-Bit Counter

ACGCAPH

ACGCAPL

Figure 2鈥?. Adaptive Clock Generator

The ACG is controlled by the following registers. Refer to section A.5.3 for details.

FUNCTIONAL REGISTER

24-bit frequency register #1

16-bit capture register

8-bit synthesizer 1 divider control register

8-bit ACG control register

24-bit frequency register #2

8-bit synthesizer 2 divider control register

ACG2FRQ2

ACG2FRQ1

ACTUAL BYTE-WIDE REGISTERS

ACG1FRQ2

ACG1FRQ1

ACGCAPH

ACG1FRQ0

ACGCAPL

ACG1DCTL

ACGCTL

ACG2FRQ0

ACG2DCTL

The main functional modules of the ACG are described in the following sections.

2.2.6.1 Programmable Frequency Synthesizer

The 24-bit ACG frequency register value is used to program the frequency synthesizer, and the value of the frequency

register can be updated by the MCU while the ACG is running. The high resolution of each frequency value

programmed allows the firmware to adjust the frequency value by +LSB or more to lock onto the USB start-of-frame

(SOF) signal and achieve a synchronous mode of operation, a necessity for streaming audio applications. The 24-bit

frequency register value is updated and used by the frequency synthesizer only when MCU writes to the ACGFRQ0

register. The proper way to update a frequency value then is to write the least significant byte (ACGFRQ0) last.

The frequency resolution of the output master clock depends on the actual frequency being output. In general, the

frequency resolution decreases with increasing output frequencies. The clock frequency of the MCLKO output signal

is calculated by using the formula:

For N

q

24 and N < 50, MCLKO frequency = 600/N MHz

For N = 50, MCLKO frequency = 12 MHz

where N is the value in the 24-bit frequency register (ACGFRQ). The value of N can range from 24 to 50. The six most

significant bits of the 24-bit frequency register are used to represent the integer portion of N, and the remaining 18

bits of the frequency register are used to represent the fractional portion of N. An example is shown below.

Example Frequency Register Calculation

Suppose the desired MCLKO frequency is 24.576 MHz. Using the above formula, N = 24.4140625 decimal. To

determine the binary value to be written to the ACGFRQ register, separately convert the integer value (24) to 6-bit

binary and the fractional value (4140625) to 18-bit binary. As a result, the 24-bit binary value is

011000.011010100000000000.

2鈥?2

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