SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

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In both modes, the on-chip C-port is used to output the received bulk data to an external device. To implement

DMA-supported transactions, the C-port must be programmed to operate in either a general-purpose (GP) mode or

an Audio Codec 鈥?7 (AC97) mode. When in the general-purpose mode, SYNC is disabled when there is no valid data

in the buffer to be output; in the AC97 mode, the time slot

valid

bits in the tag field are disabled when there is no valid

data in the buffer to be output.

Software Handshake Using MCU, UBM, and External Device

Bulk data has the lowest priority of all transfers on the USB bus. But when there is little other activity on the USB bus,

bulk transfers can achieve significant transfer rates. Bulk transfer rates then can fluctuate greatly, and for this reason

it is sometimes necessary to monitor the transfer rate of bulk transfers in order to throttle back the transfer rate when

the rate exceeds the bandwidth of the target device. The software handshake mode is provided to enable the

implementation of just such a

throttling

of data.

The following steps explain the operation of the software handshake mode.

1. The MCU initializes one of the OUT endpoints as a bulk OUT endpoint by programming the appropriate USB

endpoint configuration block. This entails programming the buffer size and buffer base address, selecting

the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and

clearing the NACK bit.

2. To configure a given DMA channel to process a given endpoint in a software handshake mode, the MCU

must

鈥?/div>

Enable the handshake mode by setting the HSKEN bit in the DMA channel control register (DMACTL0

and DMACTL1) to 1. In this same register the MCU must also program the USB endpoint direction and

endpoint number fields.

Program the DMA current buffer content register (DMABPCT0 and DMABPCT1) with the number of

bulk out packets to be handled by the DMA process without MCU intervention once the MCU has

invoked the DMA process.

Program the DMA channel time slot assignment register (DMATSH0 and DMATSH1) with the time slot

assignments to be supported by the DMA channel and the number of bytes to be transferred for each

supported time slot.

鈥?/div>

3. The MCU must also appropriately configure the C-port. (See Section 2.2.7.4 for more detail on initializing

the C-port). Note that if the C-port is placed in mode 0 (general-purpose mode) the CPTBLK bit in the codec

port interface configuration register 4 must be set to 1 to assure that SYNC is disabled when there is no valid

data in the buffer to be output.

4. Data is now ready to be received. The UBM, after receiving the bulk out packet and placing it in the

appropriate buffer, toggles the toggle bit if the double-buffer mode is set, sets the NACK bit to 1, stores the

packet data count in the data count register, and issues an interrupt to the MCU.

5. If the external device indicates that it is ready to receive data, the MCU enables the DMA process by setting

the DMAEN bit the DMA channel control register (DMACTL0 and DMACTL1). (Handshaking between the

MCU and external device will have to have taken place earlier to determine the status of the external

device).

6. Once enabled, the DMA engine proceeds to transfer the contents of the buffer(s) to the C-port for transmittal

to the external device. Data availability in the buffer(s) is determined by examining the NACK flags 鈥?which

are set to 1 when data has been received. For the double buffer case, the buffer to be used to retrieve data

for the C-port is determined by not only examining the NACK flags but also by monitoring the state of the

toggle bit. The NACK bit is cleared by the DMA logic (as opposed to the MCU) each time an entire buffer

content has been transferred to the C-port via DMA.

7. If the number of bulk out packets to be handled by the DMA process without MCU intervention is greater

than one (the number can be as high as 64K packets), multiple buffer writes take place before the DMA

process completes. Every time a data packet is written to a given buffer, the UBM generates the MCU

2鈥?9

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