SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

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during the current USB frame. A new count is derived at each USB SOF event, and is the value of the write pointer

address setting minus the read pointer address setting at the time of the USB SOF event. The MCU can read the

content of this register.

The steps required to service DMA-supported isochronous transfers are:

1. The MCU initializes an IN or OUT USB endpoint configuration block. This entails programming the buffer

size and buffer base address, setting the ISO bit, setting the number of bytes per isochronous channel,

clearing the NACK bit, and enabling the endpoint. Because the endpoint is configured as an isochronous

endpoint, the buffer configuration parameters are used to implement a circular buffer rather than one or two

linear buffers, and the size specified is the size of the single circular buffer.

2. The MCU configures the selected DMA channel. This entails:

鈥?/div>

Programming registers DMATSH0/1 and DMATSL0/1, which consists of assigning the time slots to be

used and the number of bytes to be transferred per time slot.

Programming register DMACTL0/1, which consists of setting the USB endpoint direction, selecting the

endpoint number, and setting the DMA channel enable bit DMAEN.

Programming register CPTCNF1, which consists of setting the number of time slots per audio frame

and selecting the C-port interface mode (general purpose mode, AIC mode, etc.).

Programming register CPTCNF2, which consists of setting the length of time slot 0 (number of CSCLK

serial clock cycles), setting the length of the remaining time slots (which are all the same in length), and

setting the number of data bits per time slot.

Programming register CPTCNF3, which consists of:

鈥?/div>

Setting the state of DDLY. A 1 programs a one CSCLK clock delay on the data output and data input

signals with reference to the leading edge of CSYNC. A 0 removes the delay.

Setting the state of TRSEN. A 1 sets the C-port output to the high-impedance state for those time

slots that have no valid data.

Setting the state of CSCLKP. A 1 programs the C-port to be CSCLK falling edge active (CDATO and

CSYNC transition on falling edge of CSCLK and DATI is sampled on rising edge of CSCLK). A 0

results in activity on the opposite edges of CSCLK.

Setting the state of CSYNCP. A 1 programs CSYNC to be active high. A 0 programs CSYNC to be

active low.

Setting the state of CSYNCL. A 1 programs the length of CSYNC to be the same number of CSCLK

cycles as time slot 0. A 0 programs CSYNC to be one CSCLK cycle in length.

Setting the state of BYOR. A 1 results in the DMA reversing the byte order in moving data to/from the

endpoint buffer.

Setting the state of CSCLKD. A 1 sets the CSCLK port as an input port (TAS1020A receives

CSCLK). A 0 sets the CSCLK port as an output port (TAS1020A sources CSCLK).

Setting the state of CSYNCD. A 1 sets the CSYNC port as an input port (TAS1020A receives

CSYNC). A 0 sets the CSYNC port as an output port (TAS1020A sources CSYNC).

3. The MCU configures the C-port. This entails:

鈥?/div>

Programming register CPTCNF4, which consists of:

鈥?/div>

Specifying the 4-Bit field ATSL. This field defines which time slot is to be used for secondary

communication (command/status) address and data.

Setting the state of CPTBLK. When DMA is to be used to transport USB bulk transfers to external

devices via the C-port, the C-port must be placed in either a general-purpose mode or an AC97

mode, and CPTBLK must be set to one. When the C-port is placed in the general-purpose mode, a

state of 1 for CPTBLK results in CSYNC only being present when valid data is present in the current

2鈥?1

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