SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

阅览下载纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114

frame. When the C-port is placed in the AC97 mode, a state of 1 for CPTBLK results in CSYNC

always being present, but the tag bits in time slot 0 being set to indicate the presence or absence of

data. When CPTBLK is set to 0, CSYNC and CSCLK are free running once the C-port is enabled.

鈥?/div>

Specifying the 3-Bit field DIVB. This defines the divide ratio of MCLK to CSCLK.

Programming bits 4鈥? of register CPTCTL to enable or disable the C-port transmit and receive

interrupts. Bits 1鈥? of register CPTCTL are used to select between primary and secondary codecs

when using two codecs in the AC97 mode. Bit 0 of register CPTCTL (CRST), when cleared to 0, is used

to issue resets to external devices via the CRESET output pin.

NOTE:

C-port registers CPTADR, CPTDATL and CPTDATH are accessed during run time

operation to set the address, the data, and the mode (receive (status) or command (write)) for

secondary communications. Registers CPTVSLL and CPTVSLH are only used when the AC97

mode is selected and are used to specify which time slots in the audio frame contain valid data.

Registers CPTRXCNF2, CPTRXCNF3, and CPTRXCNF4 must be initialized when the C-port

is used in the I

S mode (mode 5) to support an ADC and a DAC running at different frequencies.

2.2.7.4.1 Circular Memory Buffer Implementation

A significant feature of DMA-supported isochronous transfers is the circular memory structure used to buffer the

incoming data. In most applications, the C-port timing is derived from the USB frame rate using a soft-PLL provided

in the TAS1020A firmware. However, the USB frame rate can vary within specified boundaries, and the output phase

of the PLL can lag (or lead) the input during such variations. If a linear ping pong buffer implementation is used,

tolerance must be built into switching between buffers to accommodate all possible magnitudes of variation in the

relative timing between the input and output time references. A circular buffer topology greatly simplifies the

implementation of the buffer as the need for decision points on when to switch buffers is eliminated.

The circular buffer implementation used in TAS1020A utilizes the same endpoint start (I/OEPBBAXx) and size

(I/OEPBSIZx) assignment used by the linear buffer implementation, and the size of the circular buffer is the size

specified in I/OEPBSIZx. The circular buffer implementation does require the use of two additional registers 鈥?a read

pointer and a write pointer. These two registers are controlled by hardware, but are made available to the MCU for

debug purposes.

Circular Buffer Operation for Isochronous OUT Transactions

The operation of the circular buffer for isochronous OUT transactions is as follows.

鈥?/div>

Initially, the

read

and

write

pointers are set in hardware to the OUT endpoint start address.

As the first packet of isochronous data addressed to the endpoint is received, the UBM stores the data into

the circular buffer and updates the value of the

write

pointer by a count of one for each byte written into the

buffer.

As soon as the DMA channel detects that the read and write pointers are not the same value (data is

available), the DMA channel could begin immediately retrieving data and outputting it to the C-port.

However, the DMA channel waits until the next USB SOF is received.

Once the DMA channel has waited until the next SOF is received, the buffer contains a full packet of data.

Upon receiving SOF, the DMA channel further waits until the start of the next C-port frame and then begins

transferring the buffered data to the C-port, updating the

read

pointer by one count for each byte of data

transferred. At the C-port the data is output to the external device in accordance with the timing

requirements of the external device (8 frames for 8 kHz audio sampling, 48 frames for 48 kHz audio

sampling, etc.). The DMA channel continues to retrieve data from the buffer and output it to the C-port,

update the

read

pointer, and check the value of the

write

pointer. Should the DMA-controlled

read

pointer

value ever equal the value of the UBM-controlled write pointer, the process goes on hold and awaits the

next USB SOF, where the process again resumes.

When the UBM completes writing a packet of data into the endpoint buffer, it loads the data count value of

that packer (number of data samples, not bytes) into field DCNTX/Y of register OEPDCNTX/Yx. The register

chosen, OEPDCNTX or OEPDCNTY, is determined by the LSB of the frame count register USBFNL. An

鈥?/div>

2鈥?2

prev next

SLES003A相关型号PDF文件下载

型号

版本

描述

厂商

下载
SLES003A

英文版

Texas Instruments [USB Streaming Controller]

TI

SLES003A
SLES025A

英文版

USB Streaming Controller

TI

SLES025A
SLES025A

英文版

USB Streaming Controller

TI [Texas ...

SLES025A

SLES003A Datasheet

PDF预览

SLES003A相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

SLES003A Datasheet

PDF预览

SLES003A相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

建议反馈

PDF纠错X