SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

阅览下载纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114

鈥?/div>

C interface transmit data register empty interrupt: whenever the MCU writes to the I

C interface transmit

data register I2CDATO, it results in the hardware clearing the transmit data register empty bit TXE in the

C interface control and status register I2CCTL. When the data byte is output onto the I

C bus, the

hardware sets TXE back to logic 1 and the I

C interface transmit data register empty interrupt is issued. The

firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear the

TXE bit.

C interface receive data register full interrupt: whenever the I

C interface receive data register I2CDATI

receives a byte of data off the I

C bus, the hardware sets the receive data register full bit RXF in the I

interface control and status register I2CCTL and issues the I

C interface receive data register full interrupt.

The firmware must clear this interrupt by writing to the interrupt vector register, but this action does not clear

the RXF bit. The RXF bit in the I

C interface control and status register I2CCTL is cleared whenever the

MCU reads the contents of the I

C interface receive data register I2CDATI.

External interrupt XINT: this interrupt is provided to give a user the ability to issue interrupts from external

sources. XINT is logic 0 active. The interrupt is sampled by synchronization logic internal to the TAS1020A,

as shown in Figure 2鈥?. As Figure 2鈥? shows, XINT must be remain in an active-low state for at least one

period of the 24 MHz clock to assure that the interrupt is recognized. Also, XINT must transition to an inactive

state (logic 1) and then transition back to the active state (logic 0) if another XINT interrupt is to be

recognized. If XINT remains in the active low state, it does not result in issuing multiple XINT interrupts. The

firmware must clear this interrupt by writing to the interrupt vector register.

DMA channel 0 interrupt: this interrupt becomes active only during bulk OUT transactions utilizing DMA

channel 0 when the software handshake mode is selected (see Section 2.2.7.3.3). In this mode of operation

the programmable variable DMABPCT 鈥?registers DMABPCT0 and DMABPCT1 鈥?instructs DMA channel

0 as to how many bulk OUT packets it must handle before ceasing operation and issuing the DMA channel

0 interrupt. The firmware must clear this interrupt by writing to the interrupt vector register.

DMA channel 1 interrupt: this interrupt is identical in operation to the DMA channel 0 interrupt. Note that

the same count variable DMABPCT is used for both DMA interrupts. In fact, as described in Section 2.2.12,

only one of the two DMA channels can be active when supporting a bulk OUT transaction. 鈥?thus the need

for only one count variable DMABPCT.

鈥?/div>

The interrupts for the USB IN endpoints and USB OUT endpoints can be masked. An interrupt for a particular endpoint

occurs at the end of a successful transaction to that endpoint. A status bit for each IN and OUT endpoint also exists.

However, these status bits are read only, and therefore, these bits are intended to be used for diagnostic purposes

only. After a successful transaction to an endpoint, both the interrupt and status bit for an endpoint are asserted until

the interrupt is cleared by the MCU.

The USB function reset, USB function suspend, USB function resume, USB start-of-frame, USB pseudo start-of-

frame, USB setup stage transaction, and USB setup stage transaction over-write interrupts can all be masked. A

status bit for each of these interrupts also exists. Refer to the USB interrupt mask register and the USB status register

for more details. Note that the status bits for these interrupts are read only. For these interrupts, both the interrupt

and status bit are asserted until the interrupt is cleared by the MCU.

The codec port interface transmit data register empty, codec port interface receive data register full, I

C interface

transmit data register empty, and I

C interface receive data register full interrupts can all be masked. A status bit for

each of these interrupts also exists. Note that the status bits for these interrupts are read only. However, for these

interrupts, the status bits are not cleared automatically when the interrupt is cleared by the MCU. Refer to the codec

port interface control and status register CPTCTL and the I

C interface control and status register I2CCTL for more

details.

The external interrupt input (XINT) is logically ORed with the on-chip interrupt sources. An enable bit exists for this

interrupt in the global control register GLOBCTL. This interrupt does not have a status bit.

2鈥?8

prev next

SLES003A相关型号PDF文件下载

型号

版本

描述

厂商

下载
SLES003A

英文版

Texas Instruments [USB Streaming Controller]

TI

SLES003A
SLES025A

英文版

USB Streaming Controller

TI

SLES025A
SLES025A

英文版

USB Streaming Controller

TI [Texas ...

SLES025A

SLES003A Datasheet

PDF预览

SLES003A相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

SLES003A Datasheet

PDF预览

SLES003A相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

建议反馈

PDF纠错X