SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

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Figure 2鈥? shows the parameter settings for the AIC master or slave mode, and Section 2.2.13.1.2 provides detail

on these settings. Table 2鈥? shows the TAS1020A codec terminal assignments and the respective signal names for

the AIC mode of operation.

Table 2鈥?. Terminal Assignments for Codec Port Interface AIC Mode

TERMINAL

NO.

NAME

CSYNC

CSCLK

CDATO

CDATI

CRESET

CSCHNE

SCLK

DOUT

DIN

RESET

AIC

2.2.13.6 Bulk Mode

The TAS1020A supports bulk OUT data transactions through the codec port using one of the two available DMA

channels, but the codec port needs to be configured in AC97 or general-purpose mode to support bulk OUT

transactions. AC 鈥?7 and the general-purpose mode are the only two modes of operation that support bulk OUT

transactions, as these are the only two modes that have mechanisms in place to distinguish when valid data is or is

not being output. AC 鈥?7 uses tag bits to indicate whether or not data is valid in any given time slot. In the

general-purpose mode, no sync pulse is output if no valid data is available to be output. (In both AC 鈥?7 and the

general-purpose mode, CPTBLK must be set to logic 1 if tag bits or the sync pulse, respectively, are to indicate the

presence of valid data). See Section 2.2.7.3.3 for more detail on bulk OUT transactions using one of the two DMA

channels.

2.2.14 I

C Interface

The TAS1020A has a bidirectional two-wire serial interface that can be used to access other ICs. This serial interface

is compatible with the I

C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates. The

TAS1020A does not support all provisions of the I

C specification. The TAS1020A can only serve as a master device

on the I

C bus, but as a master device, the TAS1020A does not support a multimaster bus environment (no bus

arbitration), but can recognize wait state insertions on the bus. The I

C interface on the TAS1020A is provided to allow

access to I

C slave devices, including EEPROMs and codecs. For example, if the application program code is stored

in an EEPROM on the PCB, then the MCU downloads the code from the EEPROM to the TAS1020A on-chip RAM

using the I

C interface. Another example is the control of a codec device that uses an I

S interface for audio data

transfers and an I

C interface for control register read/write access.

2.2.14.1 Data Transfers

The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the

TAS1020A is a master only device, and therefore, the SCL signal is an output only. The SDA signal is a bidirectional

signal that uses an open-drain output to allow the TAS1020A to be wire-ORed with other devices that use open-drain

or open-collector outputs.

All read and write data transfers on the serial bus are initiated by the TAS1020A. The TAS1020A is also responsible

for generating the clock signal used for all data transfers. The data is transferred on the bus serially one bit at a time.

However, the protocol requires that the address and data be transferred in byte (8-bit) format with the most-significant

bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with

an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and

ends with the master device driving a stop condition on the bus.

The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 2鈥?1.

As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can

only change states while the SCL signal is low.

2鈥?3

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