3.4.4
Codec Port Interface Signals (I
2
S Modes) Over Recommended Operating Conditions
(unless otherwise noted)
TEST CONDITIONS
MIN
(32)FS
1/(64)FS
10
10
MAX
(64)FS
1/(32)FS
15
UNIT
MHz
ns
ns
ns
ns
Frequency, SCLK
Cycle time, SCLK
Propagation delay, SCLK falling edge to LRCLK and SDOUT
Setup time, SDIN to SCLK rising edge
CL = 50 pF
CL = 50 pF, See Note 1
CL = 50 pF
fSCLK
tcyc
tpd
tsu
th
Hold time, SDIN from SCLK rising edge
NOTE 1: Worst case duty cycle is 45/55.
SCLK
tcyc
tpd
LRCLK, SD_OUT
tsu
SD_IN
th
Figure 3鈥?. I
2
S Mode Timing Waveforms
3.4.5
Codec Port Interface Signals (General-Purpose Mode) Over Recommended Operating
Conditions (unless otherwise noted)
TEST CONDITIONS
MIN
0.125
0.040
10
MAX
25
8
15
UNIT
MHz
碌s
ns
ns
Frequency, CSCLK
Cycle time, CSCLK
Propagation delay, CSCLK to CSYNC, CDATO, CSCHNE and CRESET
Setup time, CDATI to CSCLK
CL = 50 pF
CL = 50 pF, See Note 2
CL = 50 pF
fCSCLK
tcyc
tpd
tsu
th
Hold time, CDATI from CSCLK
10
ns
NOTE 2: The timing waveforms in Figure 3-6 show the CSYNC, CDATO, CSCHNE, and CRESET signals generated with the rising edge of the
clock and the CDATI signal sampled with the falling edge of the clock. The edge of the clock used is programmable. However, the timing
characteristics are the same regardless of which edge of the clock is used.
CSCLK
tcyc
tpd
CSYNC, CDATO,
CSCHNE, CRESET
tsu
CDATI
th
Figure 3鈥?. General-Purpose Mode Timing Waveforms
3鈥?