SLES003A Datasheet

IC型号：
SLES003A
PDF描述：
Texas Instruments [USB Streaming Controller]
文件大小：
487.38KB
芯片厂家：
TI

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A.4 USB Endpoint Configuration Blocks and Data Buffer Space

A.4.1

USB Endpoint Configuration Blocks

The USB endpoint configuration space contains 16 8-byte blocks that define configuration, buffer location, buffer size,

and data count for the 16 (8 input and 8 output) USB endpoints. The MCU, UBM, and DMA all have access to these

configuration blocks.

Each of the 16 endpoints in the TAS1020A can be configured as a USB pipe endpoint by initializing the block

configuration register assigned to each endpoint. The location of the endpoint X and Y data buffers for each endpoint

is set by the value programmed into the X and Y buffer base address registers. Base addresses are octet (8-byte)

aligned. The size of the X and Y buffers is set by initializing the buffer size register. The size of the X and Y buffers

must be greater than or equal to the USB packet size associated with the endpoint. For Isochronous endpoints, the

buffer size defines the size of the single circular buffer. For IN transactions, the X and Y data count registers assigned

to each endpoint are set by the USB buffer manager (UBM) to register the size of the new data packet just received.

For OUT transactions, the X and Y data count registers assigned to each endpoint are set by the DMA logic or the

MCU to register the size of the data packet to be output. For control, interrupt, and bulk transactions, the data count

is the number of samples per transaction.

A.4.2

Data Buffer Space

The endpoint data buffer space (1304 bytes) provides rate buffering between the data traffic on the USB bus and data

traffic to and from the codecs attached to the TAS1020A. Buffers are defined in this space by base address pointers

and size descriptors in the USB endpoint configuration blocks. The MCU also has access to this space.

In order to conserve RAM memory resources on the TAS1020A, several USB-specific routines have been included

in the firmware resident in the on-chip ROM. These ROM support functions are detailed in Section 2.2.2.7. To provide

temporary variable storage for these ROM support functions, locations FA10h through FA63h (84 bytes) of the 1304

bytes of data buffer space are reserved for use by the ROM support functions. This then leaves 1220 bytes for the

endpoint buffer memories, which service applications up to 6 channels, 48 kHz sampling rate with 16 bits per sample

or 4 channels, 48-kHz sampling rate with 24 bits per sample. (If the ROM support functions are not used, the entire

block of 1304 bytes can be assigned to endpoint buffer memories.)

The values entered into the X and Y buffer base address registers are offset addresses. The lower memory address

(or Base address) of a given X (Y) buffer is determined by adding the value in the base address register (multiplied

by 8) to the base address of the block of memory assigned to the X and Y buffers. For the TAS1020A, this base

address is FA10h. However, the base address of the TUSB3200 members of the family of USB streaming audio

controllers, of which the TAS1020A is also a member, is F800h. To maintain software compatibility between family

members, the value entered into the base address register for the TAS1020A (as well as the other family members)

must be the offset from the base address F800h. For example, assume the X buffer for IN endpoint 3 is to be

established starting at address FA60h. For the TAS1020A, the offset of this address from the FA10h base address

of the block of memory assigned to the X and Y buffers is 50h. Nevertheless, the value entered into the X buffer base

address for IN endpoint 3 must be 4Ch, as F800h + 8 * 4Ch = FA60h.

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