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Two DMA channels to support streaming USB audio data to/from the codec port interface
Each channel can support a single USB isochronous endpoint
In the I
2
S mode the device can support DAC/ADCs at different sampling frequencies
A circular programmable FIFO used for isochronous audio data streaming
Configurable to support AC鈥?7 1.X, AC鈥?7 2.X, AIC or I
2
S serial interface formats
I
2
S modes can support a combination of one DAC and/or two ADCs
Can be configured as a general-purpose serial interface
Can support bulk data transfer using DMA for higher throughput
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Codec Port Interface
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I
2
C Interface
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Master only interface
Does not support a multimaster bus environment
Programmable to 100 kb/s or 400 kb/s data transfer speeds
Supports wait states to accommodate slow slaves
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General Characteristics
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High performance 48-pin TQFP Package
On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz
crystal input
Reset output available which is asserted for both system and USB reset
External MCU mode supports application firmware development
8K ROM with boot loader program and commonly used USB functions library
3.3 V core and I/O buffers
1鈥?
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