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SLES003A Datasheet

  • SLES003A

  • Texas Instruments [USB Streaming Controller]

  • 487.38KB

  • TI

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A.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 鈥?Address FFDFh)
The codec port interface configuration register 2 is used to store various control bits for the codec port interface
operation.
Bit
Mnemonic
Type
Default
BIT
7:6
MNEMONIC
TSL0L(1:0)
7
TSL0L1
R/W
0
6
TSL0L0
R/W
0
NAME
Time slot 0 length
5
BPTSL2
R/W
0
4
BPTSL1
R/W
0
3
BPTSL0
R/W
0
2
TSLL2
R/W
0
DESCRIPTION
The time slot 0 Length bits are set by the MCU to program the number of serial clock
(CSCLK) cycles for time slot 0.
00b = CSCLK cycles for time slot 0 same as other time slots
01b = 8 CSCLK cycles for time slot 0
10b = 16 CSCLK cycles for time slot 0
11b = 32 CSCLK cycles for time slot 0
The data bits per time slot bits are set by the MCU to program the number of data bits per
audio time slot. Note that this value in not used for the secondary communication address
and data time slots.
000b = 8 data bits per time slot
001b = 16 data bits per time slot
010b = 18 data bits per time slot
011b = 20 data bits per time slot
100b = 24 data bits per time slot
101b = 32 data bits per time slot
110b = reserved
111b = reserved
The time slot length bits are set by the MCU to program the number of serial clock (CSCLK)
cycles for all time slots except time slot 0.
000b = 8 CSCLK cycles per time slot
001b = 16 CSCLK cycles per time slot
010b = 18 CSCLK cycles per time slot
011b = 20 CSCLK cycles per time slot
100b = 24 CSCLK cycles per time slot
101b = 32 CSCLK cycles per time slot
110b = reserved
111b = reserved
1
TSLL1
R/W
0
0
TSLL0
R/W
0
5:3
BPTSL(2:0)
Data bits per time slot
2:0
TSLL(2:0)
Time slot length
A鈥?0

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