SLES003A Datasheet

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A.5.4.3 Codec port interface configuration register 3 (CPTCNF3 鈥?Address FFDEh)

The codec port interface configuration register 3 is used to store various control bits for the codec port interface

operation.

Bit

Mnemonic

Type

Default

BIT

7

MNEMONIC

DDLY

7

DDLY

R/W

0

6

TRSEN

R/W

0

NAME

Data delay

5

CSCLKP

R/W

1

4

CSYNCP

R/W

1

3

CSYNCL

R/W

0

2

BYOR

R/W

0

DESCRIPTION

The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of the serial

data output and input signals in reference to the leading edge of the CSYNC signal. The

MCU must clear this bit to a 0 for no delay between these signals.

The 3-state enable bit is set to a 1 by the MCU to program the hardware to set the serial

data output signal to the high-impedance state for the time slots during the audio frame that

are not valid. The MCU must clear this bit to a 0 to program the hardware to use

zero-padding for the serial data output signal for time slots during the audio frame that are

not valid.

The CSCLK polarity bit is used by the MCU to program the clock edge used for the codec

port interface frame sync (CSYNC) output signal, codec port interface serial data output

(CDATO) signal and codec port interface serial data Input (CDATI) signal. When this bit is

set to a 1, the CSYNC signal is generated with the negative edge of the codec port interface

serial clock (CSCLK) signal. Also, when this bit is set to a 1, the CDATO signal is generated

with the negative edge of the CSCLK signal and the CDATI signal is sampled with the

positive edge of the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal is

generated with the positive edge of the CSCLK signal. Also, when this bit is cleared to a 0,

the CDATO signal is generated with the positive edge of the CSCLK signal and the CDATI

signal is sampled with the negative edge of the CSCLK signal.

The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the codec port

interface frame sync (CSYNC) output signal to be active high. The MCU must clear this bit

to a 0 to program the polarity of the CSYNC output signal to be active low.

The CSYNC length bit is set to a 1 by the MCU to program the length of the codec port

interface frame sync (CSYNC) output signal to be the same number of CSCLK cycles as

time slot 0. The MCU must clear this bit to a 0 to program the length of the CSYNC output

signal to be one CSCLK cycle.

The byte order bit is used by the MCU to program the byte order for the data moved by the

DMA between the USB endpoint buffer and the codec port interface. When this bit is set to

a 1, the byte order of each audio sample is reversed when the data is moved to/from the

USB endpoint buffer. When this bit is cleared to a 0, the byte order of the each audio sample

is unchanged.

The CSCLK direction bit is set to a 1 by the MCU to program the direction of the codec port

interface serial clock (CSCLK) signal as an input to the TAS1020A device. The MCU must

clear this bit to a 0 to program the direction of the CSCLK signal as an output from the

TAS1020A device.

The CSYNC direction bit is set to a 1 by the MCU to program the direction of the codec port

interface frame sync (CSYNC) signal as an input to the TAS1020A device. The MCU must

clear this bit to a 0 to program the direction of the CSYNC signal as an output from the

TAS1020A device.

1

CSCLKD

R/W

0

0

CSYNCD

R/W

0

6

TRSEN

3-State enable

5

CSCLKP

CSCLK polarity

4

CSYNCP

CSYNC polarity

3

CSYNCL

CSYNC length

2

BYOR

Byte order

1

CSCLKD

CSCLK direction

0

CSYNCD

CSYNC direction

A鈥?1

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