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ST10F269-T3 Datasheet

  • ST10F269-T3

  • 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYT...

  • 1513.42KB

  • 160页

  • STMICROELECTRONICS   STMICROELECTRONICS

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ST10F269-T3
Figure 15 :
Block Diagram of GPT1
T2EUD
U/D
GPT1 Timer T2
2
n
n=3...10
Interrupt
Request
CPU Clock
T2IN
T2
Mode
Control
Reload
Capture
CPU Clock
2
n
n=3...10
T3IN
T3EUD
T3
Mode
Control
T3OUT
GPT1 Timer T3
U/D
Capture
Reload
T3OTL
T4IN
CPU Clock
2
n
n=3...10
T4
Mode
Control
Interrupt
Request
Interrupt
Request
GPT1 Timer T4
U/D
T4EUD
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction
(up/down)
for
each
timer
is
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overflow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is
advantageous when T3 operates in Incremental
Interface Mode.
Table 12 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 32MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the auxiliary timer
T5 in Timer and Gated Timer Mode.
Table 12 :
GPT2 Timer Input Frequencies, Resolution and Period
Timer Input Selection T5I / T6I
f
CPU
= 32MHz
000b
Pre-scaler factor
Input Freq
Resolution
Period maximum
4
8MHz
125ns
8.19ms
001b
8
4MHz
250ns
16.4ms
010b
16
2MHz
500ns
32.8ms
011b
32
1MHz
1碌s
65.5ms
100b
64
500KHz
2碌s
131ms
101b
128
250KHz
4碌s
262.1ms
110b
256
125KHz
8碌s
524.3ms
111b
512
62.5KHz
16碌s
1.05s
52/160

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