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ST10F269-T3 Datasheet

  • ST10F269-T3

  • 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYT...

  • 1513.42KB

  • 160页

  • STMICROELECTRONICS   STMICROELECTRONICS

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ST10F269-T3
12.2 - I/O鈥檚 Special Features
12.2.1 - Open Drain Mode
Some of the I/O ports of ST10F269-T3 support
the open drain capability. This programmable
feature may be used with an external pull-up
resistor, in order to get an AND wired logical
function.
This feature is implemented for ports P2, P3, P4,
P6, P7 and P8 (see respective sections), and is
controlled through the respective Open Drain
Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain
mode for each port line. If the respective control
bit ODPx.y is 鈥?鈥?(default after reset), the output
driver is in the push-pull mode. If ODPx.y is 鈥?鈥? the
open drain configuration is selected. Note that all
ODPx registers are located in the ESFR space
(See Figure 19).
PICON (F1C4h / E2h)
15
-
14
-
13
-
12
-
11
-
10
-
9
-
12.2.2 - Input Threshold Control
The standard inputs of the ST10F269-T3
determine the status of input signals according to
TTL levels. In order to accept and recognize noisy
signals, CMOS-like input thresholds can be
selected instead of the standard TTL thresholds
for all pins of Port 2, Port 3, Port 4, Port 7 and Port
8. These special thresholds are defined above the
TTL thresholds and feature a defined hysteresis to
prevent the inputs from toggling while the
respective input signal level is near the thresholds.
The Port Input Control register PICON is used to
select these thresholds for each Byte of the
indicated ports, this means the 8-bit ports P4, P7
and P8 are controlled by one bit each while ports
P2 and P3 are controlled by two bits each.
All options for individual direction and output mode
control are available for each pin, independent of
the selected input threshold. The input hysteresis
provides stable inputs from noisy or slowly
changing external signals (See Figure 20).
Reset Value: --00h
6
5
-
4
3
2
1
0
ESFR
8
-
7
P8LIN P7LIN
RW
RW
P4LIN P3HIN P3LIN P2HIN P2LIN
RW
RW
RW
RW
RW
Bit
PxLIN
Port x Low Byte Input Level Selection
0:
1:
PxHIN
0:
1:
Function
Pins Px.7...Px.0 switch on standard TTL input levels
Pins Px.7...Px.0 switch on special threshold input levels
Pins Px.15...Px.8 switch on standard TTL input levels
Pins Px.15...Px.8 switch on special threshold input levels
Port x High Byte Input Level Selection
Figure 19 :
Output Drivers in Push-pull Mode and in Open Drain Mode
External
Pullup
Pin
Pin
Q
Q
Push-Pull Output Driver
Open Drain Output Driver
57/160

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