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S25FL004D0LNAI013 Datasheet

  • S25FL004D0LNAI013

  • 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Int...

  • 792.53KB

  • 36页

  • SPANSION   SPANSION

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A d v a n c e
I n f o r m a t i o n
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure
4)
sets the Write Enable Latch (WEL)
bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program
(PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write
Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending
the instruction code, and then driving Chip Select (CS#) High.
CS#
0 1
SCK
Instruction
SI
High Impedance
SO
2 3 4 5 6 7
Figure 4. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure
5)
resets the Write Enable Latch
(WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select
(CS#) Low, sending the instruction code, and then driving Chip Select (CS#)
High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
CS#
0
1 2
3 4 5
6 7
SCK
Instruction
SI
High Impedance
SO
Figure 5.
Write Disable (WRDI) Instruction Sequence
14
S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004

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