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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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Logic Elements
With the LAB-wide
addnsub
control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [7..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack
TM
interconnect鈥檚 inherent low skew
allows clock and control signal distribution in addition to data.
Figure 2鈥?
shows the LAB control signal generation circuit.
Figure 2鈥?. LAB-Wide Control Signals
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
8
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Stratix architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See
Figure 2鈥?.
2鈥?
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005

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