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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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  • 290页

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Stratix Device Family Data Sheet
Chapter
2
Date/Version
July 2003, v2.0
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Changes Made
Added reference on page 2-73 to Figures 2-50 and 2-51 for
RCLK
connections.
Updated ranges for EPLL post-scale and pre-scale dividers on page
2-85.
Updated PLL Reconfiguration frequency from 25 to 22 MHz on page
2-87.
New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 2-96).
Updated max input frequency for
CLK[1,3,8,10]
from 462 to 500,
Table 2-24.
Renamed impedance matching to series termination throughout.
Updated naming convention for DQS pins on page 2-112 to match pin
tables.
Added DDR SDRAM Performance Specification on page 2-117.
Added external reference resistor values for terminator technology
(page 2-136).
Added Terminator Technology Specification on pages 2-137 and 2-
138.
Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for
high speed differential channels at full speed.
Wire bond package performance specification for 鈥渉igh鈥?speed
channels was increased to 624 Mbps from 462 Mbps throughout
chapter.
Updated
鈥淥perating Modes鈥?/span>
section.
Updated
鈥淭emperature Sensing Diode鈥?/span>
section.
Updated
鈥淚EEE Std. 1149.1 (JTAG) Boundary-Scan Support鈥?/span>
section.
Updated
鈥淐onfiguration鈥?/span>
section.
Updated limits for JTAG chain of devices.
Added new section,
鈥淪tratix Automated Single Event Upset (SEU)
Detection鈥?on page 3鈥?2.
Updated description of
鈥淐ustom-Built Circuitry鈥?on page 3鈥?3.
No new changes in
Stratix Device Handbook
v2.0.
Updated
Tables 4鈥?
and
4鈥?0.
Updated
Tables 4鈥?03
through
4鈥?08.
Updated
Tables 4鈥?14
through
4鈥?24.
Updated
Table 4鈥?29.
Added
Table 4鈥?30.
3
July 2005, v1.3
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January 2005, v1.2
September 2004, v1.1
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April 2003, v1.0
4
July 2005 v3.3
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Altera Corporation
Section I鈥?

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