Stratix Architecture
Figure 2鈥?7. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
Local
Interconnect
8
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
Local
Interconnect
clock_a
renwe_a
alcr_b
clocken_b
alcr_a
renwe_b
clock_b
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Figure 2鈥?8. M4K RAM Block LAB Row Interface
C4 and C8
Interconnects
R4 and R8
Interconnects
Direct link
interconnect
to adjacent LAB
10
Direct link
interconnect
to adjacent LAB
dataout
Direct link
interconnect
from adjacent LAB
M4K RAM
Block
Byte enable
Control
Signals
Clocks
Direct link
interconnect
from adjacent LAB
address
datain
8
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
Altera Corporation
July 2005
2鈥?3
Stratix Device Handbook, Volume 1