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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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  • 290页

  • ALTERA   ALTERA

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Contents
Stratix Device Handbook, Volume 1
DSP Block Interface ........................................................................................................................ 2鈥?0
PLLs & Clock Networks ..................................................................................................................... 2鈥?3
Global & Hierarchical Clocking ................................................................................................... 2鈥?3
Enhanced & Fast PLLs ................................................................................................................... 2鈥?1
Enhanced PLLs ............................................................................................................................... 2鈥?7
Fast PLLs ........................................................................................................................................ 2鈥?00
I/O Structure ...................................................................................................................................... 2鈥?04
Double-Data Rate I/O Pins ......................................................................................................... 2鈥?11
External RAM Interfacing ........................................................................................................... 2鈥?15
Programmable Drive Strength ................................................................................................... 2鈥?19
Open-Drain Output ...................................................................................................................... 2鈥?20
Slew-Rate Control ........................................................................................................................ 2鈥?20
Bus Hold ........................................................................................................................................ 2鈥?21
Programmable Pull-Up Resistor ................................................................................................ 2鈥?22
Advanced I/O Standard Support .............................................................................................. 2鈥?22
Differential On-Chip Termination ............................................................................................. 2鈥?27
MultiVolt I/O Interface ............................................................................................................... 2鈥?29
High-Speed Differential I/O Support ............................................................................................ 2鈥?30
Dedicated Circuitry ...................................................................................................................... 2鈥?37
Byte Alignment ............................................................................................................................. 2鈥?40
Power Sequencing & Hot Socketing ............................................................................................... 2鈥?40
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3鈥?
SignalTap II Embedded Logic Analyzer ............................................................................................ 3鈥?
Configuration ......................................................................................................................................... 3鈥?
Operating Modes .............................................................................................................................. 3鈥?
Configuring Stratix FPGAs with JRunner .................................................................................... 3鈥?
Configuration Schemes ................................................................................................................... 3鈥?
Partial Reconfiguration .................................................................................................................... 3鈥?
Remote Update Configuration Modes .......................................................................................... 3鈥?
Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3鈥?2
Custom-Built Circuitry .................................................................................................................. 3鈥?3
Software Interface ........................................................................................................................... 3鈥?3
Temperature Sensing Diode ............................................................................................................... 3鈥?3
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 4鈥?
Power Consumption ........................................................................................................................... 4鈥?7
Timing Model ....................................................................................................................................... 4鈥?9
Preliminary & Final Timing .......................................................................................................... 4鈥?9
Performance .................................................................................................................................... 4鈥?0
Internal Timing Parameters .......................................................................................................... 4鈥?2
External Timing Parameters ......................................................................................................... 4鈥?3
Stratix External I/O Timing .......................................................................................................... 4鈥?6
I/O Timing Measurement Methodology .................................................................................... 4鈥?0
External I/O Delay Parameters .................................................................................................... 4鈥?6
iv
Altera Corporation

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