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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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Stratix Architecture
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
occurs or just read the don鈥檛 care bits. Single-port memory supports non-
simultaneous reads and writes, but the
q[]
port will output the data once
it has been written to the memory (if the outputs are not registered) or
after the next rising edge of the clock (if the outputs are registered). For
more information, see
Chapter 2, TriMatrix Embedded Memory Blocks in
Stratix & Stratix GX Devices
of the
Stratix Device Handbook, Volume 2.
Figure 2鈥?3
shows these different RAM memory port configurations for
TriMatrix memory.
Figure 2鈥?3. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Single-Port Memory
(1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to
Figure 2鈥?3:
(1)
Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in 脳1 mode at port A and read out in 脳16
mode from port B.
Altera Corporation
July 2005
2鈥?3
Stratix Device Handbook, Volume 1

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