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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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TriMatrix Memory
M512 RAM blocks can have different clocks on its inputs and outputs.
The
wren, datain,
and write address registers are all clocked together
from one of the two clocks feeding the block. The read address,
rden,
and
output registers can be clocked by either of the two clocks driving the
block. This allows the RAM block to operate in read/write or
input/output clock modes. Only the output register can be bypassed. The
eight
labclk
signals or local interconnect can drive the
inclock,
outclock, wren, rden, inclr,
and
outclr
signals. Because of the
advanced interconnect between the LAB and M512 RAM blocks, LEs can
also control the
wren
and
rden
signals and the RAM clock, clock enable,
and asynchronous clear signals.
Figure 2鈥?5
shows the M512 RAM block
control signal generation logic.
The RAM blocks within Stratix devices have local interconnects to allow
LEs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, R8, C4, C8, and direct link
interconnects from adjacent LABs. The M512 RAM blocks can
communicate with LABs on either the left or right side through these row
interconnects or with LAB columns on the left or right side with the
column interconnects. Up to 10 direct link input connections to the M512
RAM block are possible from the left adjacent LABs and another
10 possible from the right adjacent LAB. M512 RAM outputs can also
connect to left and right LABs through 10 direct link interconnects. The
M512 RAM block has equal opportunity for access and performance to
and from LABs on either its left or right side.
Figure 2鈥?6
shows the M512
RAM block to logic array interface.
2鈥?8
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005

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