TriMatrix Memory
Figure 2鈥?6. Input/Output Clock Mode in Simple Dual-Port Mode
Notes (1), (2)
8 LAB Row
Clocks
8
data[ ]
D
Q
ENA
Memory Block
256 麓 16
Data In
512 麓 8
1,024 麓 4
2,048 麓 2
4,096 麓 1
Read Address
address[ ]
D
Q
ENA
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
D
Q
ENA
To MultiTrack
Interconnect
wraddress[ ]
D
Q
ENA
Write Address
rden
D
Q
ENA
wren
Read Enable
outclken
inclken
wrclock
D
Q
ENA
Write
Pulse
Generator
Write Enable
rdclock
Notes to
Figure 2鈥?6:
(1)
(2)
All registers shown except the
rden
register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
2鈥?8
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005