Stratix Architecture
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See
Figure 2鈥?8.
A single
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
Figure 2鈥?8. Single-Port Mode
Note (1)
8 LAB Row
Clocks
8
data[ ]
D
Q
ENA
RAM/ROM
256
脳
16
512
脳
8
1,024
脳
4
Data In
2,048
脳
2
4,096
脳
1
Data Out
D
Q
ENA
To MultiTrack
Interconnect
address[ ]
D
Q
ENA
Address
wren
Write Enable
outclken
inclken
inclock
D
Q
ENA
Write
Pulse
Generator
outclock
Note to
Figure 2鈥?8:
(1)
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Altera Corporation
July 2005
2鈥?1
Stratix Device Handbook, Volume 1