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EP1S80F1508I6ES Datasheet

  • EP1S80F1508I6ES

  • Stratix Device Family Data Sheet

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Stratix Architecture
Pipeline/Post Multiply Register
The output of 9 脳 9- or 18 脳 18-bit multipliers can optionally feed a register
to pipeline multiply-accumulate and multiply-add/subtract functions.
For 36 脳 36-bit multipliers, this register will pipeline the multiplier
function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator, a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplier. You can configure the adder/output block to use output
registers in any mode, and must use output registers for the accumulator.
The system cannot use adder/output blocks independently of the
multiplier.
Figure 2鈥?4
shows the adder and output stages.
Altera Corporation
July 2005
2鈥?1
Stratix Device Handbook, Volume 1

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