LH543601P-20 Datasheet

IC型号：
LH543601P-20
PDF描述：
256 x 36 x 2 Bidirectional FIFO
文件大小：
361.29KB
PDF页数：
43页
芯片厂家：
SHARP

阅览下载纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

LH543601

256

脳

2 Bidirectional FIFO

(CK

or CK

) whenever: the appropriate enable (EN

) is held HIGH; the appropriate request (REQ

REQ

) is held HIGH; the appropriate Read/Write control

(R/W

or R/W

) is held LOW; the FIFO address is

selected for the address inputs (A

鈥?A

or A

); and

the prescribed setup times and hold times are observed

for all of these signals. Setup times and hold times must

also be observed on the data-bus pins (D

鈥?D

35A

鈥?D

35B

Normally, the appropriate Output Enable signal (OE

or OE

) is HIGH, to disable the outputs at that port, so

that the data word present on the bus from external

sources gets stored. However, a 鈥榣oopback鈥?mode of

operation also is possible, in which the data word supplied

by the outputs of one internal FIFO is 鈥榯urned around鈥?at

the port and read back into the other FIFO. In this mode,

the outputs at the port are not disabled. To remain within

specification for all timing parameters, the Clock Cycle

Frequency must be reduced slightly below the value

which otherwise would be permissible for that speed

grade of LH543601.

When a FIFO full condition is reached, write operations

are locked out. Following the first read operation from a

full FIFO, another memory location is freed up, and the

corresponding Full Flag is deasserted (FF = HIGH). The

first write operation should begin no earlier than a First

Write Latency (t

FWL

) after the first read operation from a

full FIFO, to ensure that correct read data are retrieved.

FIFO Read

Port A reads from FIFO #2, and Port B reads from FIFO

#1. A read operation is initiated on the rising edge of

a clock (CK

or CK

) whenever: the appropriate enable

(EN

or EN

) is held HIGH; the appropriate request

(REQ

or REQ

) is held HIGH; the appropriate

Read/Write control (R/W

or R/W

) is held HIGH;

the FIFO address is selected for the address inputs

鈥?A

or A

); and the prescribed setup times and

hold times are observed for all of these signals. Read data

Table 1. Resource-Register Addresses

RESOURCE

PORT A

OPERATIONAL DESCRIPTION

Reset

The device is reset whenever the asynchronous Reset

(RS) input is taken LOW, and at least one rising edge and

one falling edge of both CK

and CK

occur while RS is

LOW. A reset operation is required after power-up, before

the first write operation may occur. The LH543601 is fully

ready for operation after being reset. No device program-

ming is required if the default states described below are

acceptable.

A reset operation initializes the read-address and

write-address pointers for FIFO #1 and FIFO #2 to those

FIFO鈥檚 first physical memory locations. If the respective

outputs are enabled, the initial contents of these first

locations appear at the outputs. FIFO and mailbox status

flags are updated to indicate an empty condition. In

addition, the programmable-status-flag offset values are

initialized to eight. Thus, the AE

/AE

flags get asserted

within eight locations of an empty condition, and the

/AF

flags likewise get asserted within eight locations

of a full condition, for FIFO #1/FIFO #2 respectively.

Bypass Operation

During reset (whenever RS is LOW) the device acts

as a registered transceiver, bypassing the internal FIFO

memories. Port A acts as the master port. A write or read

operation on Port A during reset transfers data directly to

or from Port B. Port B is considered to be the slave, and

cannot perform write or read operations independently on

its own during reset.

The direction of the bypass data transmission is deter-

mined by th R/W

control input, which does not get

overridden by the RS input. Here, a 鈥榳rite鈥?operation

means passing data from Port A to Port B, and a 鈥榬ead鈥?/div>

operation means passing data from Port B to Port A.

The bypass capability may be used to pass initializa-

tion or configuration data directly between a master proc-

essor and a peripheral device during reset.

Address Modes

Address pins select the device resource to be

accessed by each port. Port A has three resource-regis-

ter-select inputs, A

, A

, and A

, which select between

FIFO access, mailbox-register access, control-register

access (write only), and programmable flag-offset-value-

to select between FIFO access or mailbox-register ac-

cess.

The status of the resource-register-select inputs is

sampled at the rising edge of an enabled clock (CK

). Resource-register select-input address definitions

are summarized in Table 1.

FIFO Write

Port A writes to FIFO #1, and Port B writes to FIFO #2.

A write operation is initiated on the rising edge of a clock

FIFO

Mailbox

, AE

, AF

, AE

Flag Offsets

Control Register (Parity Mode)

Flag Offset Register

RESOURCE

PORT B

FIFO

Mailbox

prev next

LH543601P-20相关型号PDF文件下载

型号

版本

描述

厂商

下载
LH5420

英文版

256 x 36 x 2 Bidirectional FIFO

SHARP

LH5420
LH5424

英文版

5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...

LH5424
LH5424

英文版

5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs...

SIEMENS [S...

LH5424
LH5464

英文版

5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED

LH5464
LH5464

英文版

5 mm T1 3/4 LED, Diffused Super-Bright, Hyper-Red GaAIAs-LED

SIEMENS [S...

LH5464
LH5481

英文版

Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

SHARP

LH5481
LH5481

英文版

Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

SHARP [Sha...

LH5481
LH5491

英文版

Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

SHARP

LH5491
LH5491

英文版

Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

SHARP [Sha...

LH5491
LH5493

英文版

4K x 9 Parallel-to Serial FIFO

SHARP

LH5493
LH5496

英文版

CMOS 512 X 9 FIFO

SHARP

LH5496
LH5496

英文版

CMOS 512 X 9 FIFO

SHARP [Sha...

LH5496
LH5496

英文版

CMOS 512 x 9 FIFO

SHARP [Sha...

LH5496
LH5497

英文版

CMOS 1K X 9 FIFO

SHARP

LH5497
LH5498

英文版

CMOS 2K X 9 FIFO

SHARP

LH5498
LH5499

英文版

CMOS 4K X 9 FIFO

SHARP

LH5499
LH5496H

英文版

CMOS 512 X 9 FIFO

SHARP

LH5496H
LH5496H

英文版

CMOS 512 x 9 FIFO

SHARP [Sha...

LH5496H
LH5496H

英文版

CMOS 512 X 9 FIFO

SHARP [Sha...

LH5496H
LH5496U

英文版

CMOS 512 X 9 FIFO

SHARP

LH5496U

LH543601P-20 Datasheet

PDF预览

LH543601P-20相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

LH543601P-20 Datasheet

PDF预览

LH543601P-20相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

建议反馈

PDF纠错X