LH543601
256
脳
36
脳
2 Bidirectional FIFO
TIMING DIAGRAMS (cont鈥檇)
CK
A
(CK
B
)
t
RWS
t
RWH
R/W
A
(R/W
B
)
t
ES
t
EH
EN
A
(EN
B
)
t
RQS
t
RQH
REQ
A
(REQ
B
)
t
EF
t
EF
EF
2
(EF
1
)
CK
B
(CK
A
)
t
RWS
t
RWH
R/W
B
(R/W )
A
t
ES
t
EH
EN
B
(EN
A
)
t
RQS
t
RQH
REQ
B
(REQ
A
)
NOTES:
1. A
2A
, A
1A
, and A
0A
all are held HIGH for FIFO access at Port A.
A
0B
is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock edges,
whereas deassertion of the Empty Flags is controlled by falling
clock edges.
543601-1
Figure 15. Empty Flag Timing
24