256
脳
36
脳
2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS
t
RS
RS
t
RSS
t
RSH
t
RSS
CK
A
t
ES
t
EH
t
ES
t
EH
EN
A
t
RQS
t
RQH
t
RQS
t
RQH
REQ
A
t
RSS
t
RSH
t
RSS
CK
B
t
ES
t
EH
t
ES
t
EH
EN
B
t
RQS
t
RQH
t
RQS
t
RQH
REQ
B
t
RF
EF, AE
t
RF
HF, AF, FF, MBF
NOTES:
1. RS overrides all other input signals, except for R/W
A
, EN
A
, and REQ
A
. It operates
asynchronously. RS operates whether or not EN
A
and/or EN
B
are asserted. However,
at least one rising edge and one falling edge of both CK
A
and CK
B
must occur while
RS is being asserted (is LOW), with timing as defined by t
RSS
and t
RSH
.
2. Otherwise, t
RSS
, t
RSH
need not be met unless the rising edge of CK
A
and/or CK
B
occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH).
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset.
543601-26
Figure 8. Reset Timing
17