LH543601
256
脳
36
脳
2 Bidirectional FIFO
TIMING DIAGRAMS (cont鈥檇)
RS
t
RSS
t
RSH
CK
A
t
RWS
t
RWH
t
RWS
t
RWH
R/W
A
t
ES
t
EH
t
ES
t
EH
EN
A
t
RQS
t
RQH
t
RQS
t
RQH
REQ
A
OE
B
t
BS
t
BH
t
A
t
ZX
t
BA
t
OH
D
0B
- D
35B
BYPASS IN
BYPASS DATA OUT
OE
A
t
BA
t
OH
t
XZ
t
BS
t
BH
D
0A
- D
35A
PREVIOUS DATA
BYPASS
OUT
BYPASS
IN
NOTES:
1. t
RSS
, t
RSH
need not be met unless the rising edge of CK
A
or CK
B
occurs while that clock is enabled.
2. Port A is considered the master port for bypass operation. Thus, CK
A
, R/W
A
, EN
A
, and REQ
A
control
the transmission of data between ports at reset.
543601-27
Figure 9. Data Bypass Timing
18