256
脳
36
脳
2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont鈥檇)
WRITE TO
MAILBOX #1
CK
A
t
RWS
t
RWH
t
RWS
t
RWH
READ FROM
MAILBOX #2
R/W
A
t
ES
t
EH
t
ES
t
EH
EN
A
t
RQS
t
RQH
t
RQS
t
RQH
REQ
A
t
AS
t
AH
t
AS
t
AH
A
2A
t
AS
t
AH
t
AS
t
AH
A
1A
t
AS
t
AH
t
AS
t
AH
A
0A
t
MBF
MBF
2
MAXIMUM OF 2 CK
B
CYCLES LATENCY
CK
B
t
MBF
MBF
1
OE
A
t
A
t
DS
t
DH
t
ZX
t
A
t
OH
D
0A
- D
35A
MAILBOX IN
MAILBOX OUT
NOTES:
1. Both edges of MBF
2
are synchronized to the Port A clock, CK
A
.
2. Both edges of MBF
1
are synchronized to the Port B clock, CK
B
.
3. There is a maximum of two CK
B
clock cycles of synchronization latency before MBF
1
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
543601-22
Figure 12. Port A Mailbox Access
21