256
脳
36
脳
2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont鈥檇)
LOAD FLAG
POSITIONS
CK
A
t
RWS
t
RWH
READ FLAG
POSITIONS
t
RWS
t
RWH
R/W
A
t
ES
t
EH
t
ES
t
EH
EN
A
t
RQS
t
RQH
t
RQS
t
RQH
REQ
A
t
AS
t
AH
t
AS
t
AH
A
2A
t
AS
t
AH
t
AS
t
AH
A
1A
t
AS
t
AH
t
AS
t
AH
A
0A
OE
A
t
A
t
DS
t
DH
t
ZX
t
A
t
OH
D
0A
- D
35A
FLAG DATA IN
FLAG DATA OUT
t
RF
AE
1
, AE
2
, AF
1
, AF
2
NOTES:
1. For valid flag address codes and data formats, see Table 3.
2. If flag status is altered by flag programming, the updated flags will be valid within a time t
RF.
3. The Control Register may be loaded as shown here, with A
2A
, A
1A
, A
0A
= HLL. However, it
is not available for reading back.
543601-18
Figure 14. Flag Programming
23