LH543601
256
脳
36
脳
2 Bidirectional FIFO
TIMING DIAGRAMS (cont鈥檇)
CK
B
t
RWS
R/W
B
t
ES
t
EH
t
ES
t
EH
t
ES
EN
B
t
RQS
t
RQH
t
RQS
t
RQH
t
RQS
REQ
B
t
RSH
t
RS
t
RSS
RT
1
t
RSH
t
RSS
CK
A
t
RWS
R/W
A
t
ES
t
EH
t
ES
t
EH
t
ES
EN
A
t
RQS
t
RQH
t
RQS
t
RQH
t
RQS
REQ
A
NOTES:
1. t
RSS
and t
RSH
need not be met unless a rising edge of CK
A
or CK
B
occurs while that clock is enabled.
2. t
RSS
is the time needed to deassert RT
1
before returning to a normal FIFO cycle.
3. t
RSH
is the time needed before asserting RT
1
after a normal FIFO cycle.
4. Read and write operations to FIFO #1 should be disabled while RT
1
is being asserted.
543601-21
Figure 21. FIFO #1 Retransmit
30