LH543601
256
脳
36
脳
2 Bidirectional FIFO
TIMING DIAGRAMS (cont鈥檇)
CK
B
t
RWH
t
RWS
R/W
B
t
EH
t
ES
t
EH
t
ES
t
RWH
t
RWS
EN
B
t
RQH
t
RQS
REQ
B
t
DH
t
DS
D
0B
- D
35B
N1
t
RQH
t
RQS
t
DH
t
DS
N2
t
EF
EF
2
t
FRL
t
EF
CK
A
t
RWH
t
RWS
R/W
A
t
EH
t
ES
EN
A
t
RQH
t
RQS
t
RQH
t
RQS
t
EH
t
ES
t
RWH
t
RWS
REQ
A
t
A
t
OH
D
0A
- D
35A
PREVIOUS DATA
N1
t
A
t
OH
N2
NOTES:
1. A
2A
, A
1A
, A
0A
, and A
0B
are all held HIGH for FIFO access.
2. OE
B
is held HIGH.
3. OE
A
is held LOW.
4. t
FRL
(First Read Latency) - The first read following an empty condition
may begin no earlier than t
FRL
after the first write to an empty FIFO,
to ensure that valid read data is retrieved.
543601-17
Figure 23. FIFO #2 Write and Read Operation in
Near-Empty Region
32