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LH543601P-20 Datasheet

  • LH543601P-20

  • 256 x 36 x 2 Bidirectional FIFO

  • 361.29KB

  • 43页

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LH543601
256
脳
36
脳
2 Bidirectional FIFO
TIMING DIAGRAMS (cont鈥檇)
Outside the 'almost-empty' region,
acknowledge is continuous
for a continuous request.
Starting at the third cycle after entering the
'almost-empty' region, acknowledge
occurs on every third cycle to prevent underrun
of the empty condition.
*
CK
A
(CK
B
)
t
RWS
*
*
*
*
R/W
A
(R/W
B
)
t
RQS
REQ
A
(REQ
B
)
t
ACK
t
ACK
t
ACK
t
ACK
ACK
A
(ACK
B
)
1
t
AE
AE
2
(AE
1
)
2
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
Indicates where a read would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
*
543601-9
Figure 31. Read Request/Acknowledge Handshake
40

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