24LC512 Datasheet

IC型号：
24LC512
PDF描述：
512K I?C? CMOS Serial EEPROM
文件大小：
386.22KB
PDF页数：
26页
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24AA512/24LC512/24FC512

7.0

ACKNOWLEDGE POLLING

FIGURE 7-1:

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W =

0).

If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, then the Start bit and control byte

must be resent. If the cycle is complete, then the device

will return the ACK and the master can then proceed

with the next Read or Write command. See Figure 7-1

for flow diagram.

ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W =

Did Device

Acknowledge

(ACK =

0)?

YES

Operation

铮?/div>

2004 Microchip Technology Inc.

DS21754E-page 11

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