CED73A3/CEU73A3
V
GS
, Gate to Source Voltage (V)
10
V
DS
=15V
I
D
=20A
10
3
I
D
, Drain Current (A)
8
R
DS(ON)
Limit
10
2
6
4
100碌s
1ms
10ms
100ms
DC
10
1
2
0
0
7
14
21
28
35
10
0
T
C
=25 C
T
J
=150 C
Single Pulse
10
-1
6
10
0
10
1
10
2
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
1. R
胃JA
(t)=r (t) * R
胃JA
2. R
胃JA
=See Datasheet
3. T
JM-
T
A
= P* R
胃JA
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
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