CY7C09279V-9AC Datasheet

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CY7C09269V/79V/89V

CY7C09369V/79V/89V

Pin Configurations

(continued)

100-Pin TQFP (Top View)

CNTENR

CNTENL

ADSR

CLKR

ADSL

CLKL

GND

GND

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

75

74

73

72

71

70

69

68

67

66

A8L

A7L

A6L

A5L

A4L

A3L

A2L

A1L

A0L

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

A9L

A10L

A11L

A12L

A13L

[10]

[11]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A8R

A9R

A10R

A11R

A12R

A13R

A14R

A15R

LBR

UBR

CE0R

CE1R

CNTRSTR

R/WR

GND

OER

FT/PIPER

I/O17R

GND

I/O16R

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

[10]

[11]

A14L

A15L

LBL

UBL

CE0L

CE1L

CY7C09389V (64K x 18)

CY7C09379V (32K x 18)

CY7C09369V (16K x 18)

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CNTRSTL

R/WL

OEL

VCC

FT/PIPEL

I/O17L

I/O16L

GND

I/O15L

I/O14L

I/O13L

1/012L

I/O11L

I/O10L

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

I/O1L

I/O0L

I/01R

I/O0R

I/O2R

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

Selection Guide

CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V

CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V

-6

[1, 2]

-7

[2]

-9

-12

f

MAX2

(MHz) (Pipelined)

Max. Access Time (ns)

(Clock to Data,

Pipelined)

Typical Operating

Current I

CC

(mA)

Typical Standby Current

for I

SB1

(mA) (Both

Ports TTL Level)

Typical Standby Current

for I

SB3

(碌A) (Both Ports

CMOS Level)

100

6.5

83

7.5

67

9

50

12

175

25

155

25

135

20

I/O9R

I/10R

VCC

GND

GND

VCC

115

20

10

碌A

10

碌A

10

碌A

10

碌A

Notes:

10. This pin is NC for CY7C09369V.

11. This pin is NC for CY7C09369V and CY7C09379V.

Document #: 38-06056 Rev. **

Page 3 of 19

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