DS1609
DUAL PORT RAM TIMING: READ CYCLE
DURING READ CYCLE WE = V
IH
AD0 鈥?AD7
t
AS
ADDRESS VALID
DON鈥橳 CARE
DATA OUT VALID
t
AH
CE
t
CEZ
t
COE
t
OEA
OE
t
OEZ
NOTES:
1. During read cycle the address must be off the bus prior to t
OEA
minimum to avoid bus contention.
2. Read cycles are terminated by the first occurring rising edge of OE or CE.
DUAL PORT RAM TIMING: WRITE CYCLE
DURING WRITE CYCLE OE = V
IH
AD0 鈥?AD7
t
AS
ADDRESS VALID
DON鈥橳 CARE
DATA IN VALID
t
AH
CE
t
CWE
t
DS
WE
t
WP
t
DH
NOTE:
1. Write cycles are terminated by the first occurring edge of WE or CE.
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