PIC16C74B Datasheet

IC型号：
PIC16C74B
PDF描述：
8-Bit CMOS Microcontrollers with A/D Converter
文件大小：
2156.20KB
PDF页数：
184页
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PIC16C63A/65B/73B/74B

9.2

Compare Mode

9.2.4

SPECIAL EVENT TRIGGER

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

鈥?Driven high

鈥?Driven low

鈥?Remains unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special event trigger output of CCP2 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled).

Note:

The special event trigger from the

CCP1and CCP2 modules will not set inter-

rupt flag bit TMR1IF (PIR1<0>).

FIGURE 9-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

9.3

PWM Mode (PWM)

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

CCPR1H CCPR1L

Output

Logic

RC2/CCP1

Match

TRISC<2>

Output Enable CCP1CON<3:0>

Mode Select

Comparator

TMR1H

TMR1L

In Pulse Width Modulation mode, the CCPx pin pro-

duces up to a 10-bit resolution PWM output. Since the

CCP1 pin is multiplexed with the PORTC data latch, the

TRISC<2> bit must be cleared to make the CCP1 pin

an output.

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

Figure 9-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 9.3.3.

9.2.1

CCP PIN CONFIGURATION

FIGURE 9-3:

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the PORTC

I/O data latch.

CCPR1L

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

9.2.2

TIMER1 MODE SELECTION

CCPR1H (Slave)

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

Comparator

RC2/CCP1

TMR2

(Note 1)

TRISC<2>

Clear Timer,

CCP1 pin and

latch D.C.

9.2.3

SOFTWARE INTERRUPT MODE

Comparator

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCPIF bit is set, causing

a CCP interrupt (if enabled).

PR2

Note 1:

8-bit timer is concatenated with 2-bit internal Q clock,

or 2 bits of the prescale, to create 10-bit time-base.

DS30605C-page 52

铮?/div>

2000 Microchip Technology Inc.

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