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PIC18F2431 Datasheet

  • PIC18F2431

  • 采用纳瓦技术、高性能PWM 和A/D 的 28/40/44 引脚增强型闪存单片...

  • 6808.04KB

  • 396页

  • MICROCHIP

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PIC18F2331/2431/4331/4431
8.0
8.1
8 X 8 HARDWARE MULTIPLIER
Introduction
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
鈥?Higher computational throughput
鈥?Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2331/2431/4331/4431 devices. By making
the multiply a hardware operation, it completes in a
single instruction cycle. This is an unsigned multiply
that gives a 16-bit result. The result is stored into the
16-bit product register pair (PRODH:PRODL). The
multiplier does not affect any flags in the Status
register.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Multiply Method
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
24
52
36
Cycles
(Max)
69
1
91
6
242
24
254
36
Time
@ 40 MHz
6.9
碌s
100 ns
9.1
碌s
600 ns
24.2
碌s
2.4
碌s
25.4
碌s
3.6
碌s
@ 10 MHz
27.6
碌s
400 ns
36.4
碌s
2.4
碌s
96.8
碌s
9.6
碌s
102.6
碌s
14.4
碌s
@ 4 MHz
69
碌s
1
碌s
91
碌s
6
碌s
242
碌s
24
碌s
254
碌s
36
碌s
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
8.2
Operation
EXAMPLE 8-1:
MOVF
MULWF
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument鈥檚 Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
ARG1, W
ARG2
EXAMPLE 8-2:
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
ARG1,
ARG2
8 x 8 SIGNED MULTIPLY
ROUTINE
W
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
铮?/div>
2003 Microchip Technology Inc.
Preliminary
DS39616B-page 89

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