PIC18F2331/2431/4331/4431
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in
Power-Managed mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Interrupt to CPU
Vector to Location
0008h
GIEH/GIE
IPE
IPEN
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
PSPIF
PSPIE
PSPIP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
Interrupt to CPU
Vector to Location
0018h
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
GIEL\PEIE
Additional Peripheral Interrupts
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS39616B-page 92
Preliminary
铮?/div>
2003 Microchip Technology Inc.
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