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SC16C654BIBM Datasheet

  • SC16C654BIBM

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byt...

  • 292.47KB

  • 58页

  • PHILIPS

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Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C654B/654DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the receive holding
register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTA to INTD outputs, and the package operates with interrupt outputs
enabled continuously.
6.9 Programmable baud rate generator
The SC16C654B/654DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate
of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supporting a 5 Mbit/s data rate. The SC16C654B/654DB can be con铿乬ured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XTAL1 and XTAL2 pins; see
Figure 10.
Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates; see
Table 7.
XTAL1
XTAL2
XTAL1
XTAL2
1.5 k鈩?/div>
X1
1.8432 MHz
X1
1.8432 MHz
C1
22 pF
C2
33 pF
C1
22 pF
C2
47 pF
002aaa870
Fig 10. Crystal oscillator connection
The generator divides the input 16脳 clock by any divisor from 1 to (2
16
鈭?/div>
1). The
SC16C654B/654DB divides the basic external clock by 16. Further division of this 16脳
clock provides two table rates to support low and high data rate applications using the
same system design. After a hardware reset and during initialization, the
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
20 of 58

SC16C654BIBM 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 1250

  • IrDA

  • SC16C654BIBM,157

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