Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
FIFO Control Register bits description
鈥ontinued
Description
Transmit operation in mode 鈥?鈥?
When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
the trigger level has been reached.
Receive operation in mode 鈥?鈥?
When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY pin will
go to a logic 0. Once activated, it will go to a logic 1 after there are no
more characters in the FIFO.
Table 10:
Bit
3
(cont.)
Symbol
FCR[3]
(continued)
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO.
This bit must be a 鈥?鈥?/div>
when other FCR bits are written to, or they will not be
programmed.
Table 11:
FCR[7]
0
0
1
1
Table 12:
FCR[5]
0
0
1
1
RX trigger levels
FCR[6]
0
1
0
1
TX trigger levels
FCR[4]
0
1
0
1
TX FIFO trigger level (# of characters)
08
16
32
56
RX FIFO trigger level
08
16
56
60
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
28 of 58
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