library lpm;
use lpm.lpm_components.all;
library ieee;
use ieee.std_logic_1164.all;
entity lpm_inst is
port (clock, we: in std_logic;
data : in std_logic_vector(3 downto 0);
address : in std_logic_vector(3 downto 0);
q : out std_logic_vector (3 downto 0));
end lpm_inst;
architecture arch1 of lpm_inst is
begin
I0 : lpm_ram_dq
generic map (LPM_WIDTH => 4,
LPM_WIDTHAD => 4,
LPM_TYPE => "LPM_RAM_DQ")
port map (data => data,
address => address,
we => we,
inclock => clock,
outclock => clock,
q => q);
end arch1;

其实Synplify可以识别出你的ram然后自动的用lpm代替，但是好像对xilinx的不大好用