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ADC08D1500EVAL Datasheet

  • ADC08D1500EVAL

  • High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Conver...

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  • 33页

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ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter
PRELIMINARY
June 2005
ADC08D1500
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D
Converter
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC08D1500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.7 GSPS. Consuming
a typical 1.9 Watts at 1.5 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.25 ENOB with a 748 MHz input signal
and a 1.5 GHz sample rate while providing a 10
-18
B.E.R.
Output formatting is offset binary and the LVDS digital out-
puts are compliant with IEEE 1596.3-1996, with the excep-
tion of an adjustable common mode voltage between 0.8V
and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40藲C
鈮?/div>
T
A
鈮?/div>
+85藲C) temperature range.
Features
n
n
n
n
n
n
n
n
n
Internal Sample-and-Hold
Single +1.9V
卤
0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Key Specifications
n
n
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n
n
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Resolution
Max Conversion Rate
Bit Error Rate
ENOB
@
748 MHz Input
DNL
Power Consumption
鈥?Operating
鈥?Power Down Mode
8 Bits
1.5 GSPS (min)
10
-18
(typ)
7.25 Bits (typ)
卤
0.15 LSB (typ)
1.9 W (typ)
3.5 mW (typ)
Applications
n
n
n
n
n
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
Block Diagram
20152153
漏 2005 National Semiconductor Corporation
DS201521
www.national.com

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