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ADC08D1500EVAL Datasheet

  • ADC08D1500EVAL

  • High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Conver...

  • 861.71KB

  • 33页

  • NSC

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ADC08D1500
2.0 Applications Information
(Continued)
Driving the V
BG
pin to change the reference voltage.
As
mentioned in Section 2.1, the reference voltage is intended
to be fixed to provide one of two different full-scale values
(650 mV
P-P
and 870 mV
P-P
). Over driving this pin will not
change the full scale value, but can be used to change the
LVDS common mode voltage from 0.8V to 1.2V by tying the
V
BG
pin to V
A
.
Driving the clock input with an excessively high level
signal.
The ADC input clock level should not exceed the
level described in the Operating Ratings Table or the input
offset could change.
Inadequate input clock levels.
As described in Section 2.3,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction
of an input offset.
Using a clock source with excessive jitter, using an
excessively long input clock signal trace, or having
other signals coupled to the input clock signal trace.
This will cause the sampling interval to vary, causing exces-
sive output noise and a reduction in SNR performance.
Failure to provide adequate heat removal.
As described in
Section 2.6.2, it is important to provide adequate heat re-
moval to ensure device reliability. This can either be done
with adequate air flow or the use of a simple heat sink built
into the board. The backside pad should be grounded for
best performance.
www.national.com
32

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